Pinout Description
Last updated
Last updated
A 15 pin 1 mm Pitch FFC connector is used for the transfer of the IĀ²C and MIPI CSI-2 communication. The connector is desinged for FFC/FPC cables with contacts on the same side facing upwards on the B101.
Pin | Description | Note |
---|---|---|
This connector was added on the B101 in revision 4 and on the B102 in revision 2
Pin | Description | Note |
---|---|---|
Pin | Description | Note |
---|---|---|
1
GND
Ground (0V)
2
CSI_D0_N
CSI-2 data lane 0
3
CSI_D0_P
CSI-2 data lane 0
4
GND
Ground (0V)
5
CSI_D1_N
CSI-2 data lane 1
6
CSI_D1_P
CSI-2 data lane 1
7
GND
Ground (0V)
8
CSI_D2_N
CSI-2 data lane 2
9
CSI_D2_P
CSI-2 data lane 2
10
GND
Ground (0V)
11
CSI_D2_N
CSI-2 data lane 3
12
CSI_D2_P
CSI-2 data lane 3
13
GND
Ground (0V)
14
CSI_CLK_N
CSI-2 clock
15
CSI_CLK_P
CSI-2 clock
16
GND
Ground (0V)
17
CAM_PWDN
18
CAM_MCLK
19
GND
Ground (0V)
20
I2C_SCL
I2C clock (3.3V level)
21
I2C_SDA
I2C data (3.3V level)
22
3.3V
V3.3 power out (on-board LDO with 300mA max. current)
1
V3.3
V3.3 power out (on-board LDO with 300mA max. current)
2
RESET
hardware reset to the TC358743 HDMI to CSI-2 bridge (3.3V level, low active)
3
CABLE
Cable detect: high (3.3V) is HDMI cable is plugged in
4
A-MCLK
I2S audio master clock (3.3V level)
5
A-DATA
I2S audio data out (3.3V level)
6
A-BCK
I2S audio bit clock (3.3V level)
7
A-LRCK
I2S audio word clock (3.3V level)
8
GND
Ground (0V)
1
GND
Ground (0V)
2
CSI_D0_N
CSI-2 data lane 0
3
CSI_D0_P
CSI-2 data lane 0
4
GND
Ground (0V)
5
CSI_D1_N
CSI-2 data lane 1
6
CSI_D1_P
CSI-2 data lane 1
7
GND
Ground (0V)
8
CSI_CLK_N
CSI-2 clock
9
CSI_CLK_P
CSI-2 clock
10
GND
Ground (0V)
11
CAM_PWDN
12
CAM_MCLK
13
I2C_SCL
I2C clock (3.3V level)
14
I2C_SDA
I2C data (3.3V level)
15
3.3V
V3.3 power out (on-board LDO with 300mA max. current)