Loading...
Loading...
Loading...
SKU | Description |
---|---|
Auvidea can take no responsibility for the accuracy or completeness of any information presented in an exported PDF document as the export feature is developed, managed and maintained by GitBook. Those export mechanisms are subject to change without interaction by Auvidea. Please note that Auvidea includes this version table to identify the document and reference changes.
The J20 is a CSI adapter board for the devkit camera connector. It allows connecting up to 6 CSI-2 cameras, each 2 Lanes. This board is compatible with the:
TX1 Devkit (SKU: †)
AGX Xavier Devkit (SKU: †)
AGX Orin Devkit (SKU: 945-13730-0055-000)
† -> End of life for this product is already reached
Keep in mind that the camera serial interfaces may changes if you connect it to other devkit boards than the TX1 because the J20 was designed for the TX1 devkit and other most recent devkit from Nvidia are using a slightly different CSI mapping.
Each I²C Bus that is populated on that connector connects to 2 camera ports. Therefore, the J20 implements an I²C address translation to avoid an address conflict if the same camera is connected to both connectors.
The following table gives a brief overview over the translation.
Version | Changes |
---|---|
Version | Changes |
---|---|
port | I2C | translation | Pi camera 1.3 | Pi camera 2.1 | B101/B102 |
---|---|---|---|---|---|
1.0
Internal verification
1.1
Initial release on Gitbook
38223-1
very limited supply patch for power up reset of GPIO port expander
38223-2
Fixed bugs from previous revision
J1_1
0
-
0x36
0x64
0x0F
J1_2
6
-
0x36
0x64
0x0F
J1_3
2
-
0x36
0x64
0x0F
J2_1
0
✓
0x34
0x12
0x0D
J2_2
6
✓
0x34
0x12
0x0D
J2_3
2
✓
0x34
0x12
0x0D
70723
Standard version
Pin | Description | Note |
---|---|---|
Pin | Description | Note |
---|---|---|
Pin | Description | Note |
---|---|---|
Pin | Description | Note |
---|---|---|
Pin | Description | Note |
---|---|---|
Pin | Description | Note |
---|---|---|
Pin | name | description |
---|---|---|
1
GND
Ground (0V)
2
CSI_A_D0_N
CSI-2 A data lane 0
3
CSI_A_D0_P
CSI-2 A data lane 0
4
GND
Ground (0V)
5
CSI_A_D1_N
CSI-2 A data lane 1
6
CSI_A_D1_P
CSI-2 A data lane 1
7
GND
Ground (0V)
8
CSI_A_CLK_N
CSI-2 A clock
9
CSI_A_CLK_P
CSI-2 A clock
10
GND
Ground (0V)
11
CAM_A_PWDN
12
CAM_A_MCLK
13
I2C_SCL_1
I2C clock (3.3V level)
14
I2C_SDA_1
I2C data (3.3V level)
15
3.3V
V3.3 power out
1
GND
Ground (0V)
2
CSI_B_D0_N
CSI-2 B data lane 0
3
CSI_B_D0_P
CSI-2 B data lane 0
4
GND
Ground (0V)
5
CSI_B_D1_N
CSI-2 B data lane 1
6
CSI_B_D1_P
CSI-2 B data lane 1
7
GND
Ground (0V)
8
CSI_B_CLK_N
CSI-2 B clock
9
CSI_B_CLK_P
CSI-2 B clock
10
GND
Ground (0V)
11
CAM_B_PWDN
12
CAM_B_MCLK
13
I2C_SCL_1
I2C clock (3.3V level)
14
I2C_SDA_1
I2C data (3.3V level)
15
3.3V
V3.3 power out
1
GND
Ground (0V)
2
CSI_C_D0_N
CSI-2 C data lane 0
3
CSI_C_D0_P
CSI-2 C data lane 0
4
GND
Ground (0V)
5
CSI_C_D1_N
CSI-2 C data lane 1
6
CSI_C_D1_P
CSI-2 C data lane 1
7
GND
Ground (0V)
8
CSI_C_CLK_N
CSI-2 C clock
9
CSI_C_CLK_P
CSI-2 C clock
10
GND
Ground (0V)
11
CAM_C_PWDN
12
CAM_C_MCLK
13
I2C_SCL_3
I2C clock (3.3V level)
14
I2C_SDA_3
I2C data (3.3V level)
15
3.3V
V3.3 power out
1
GND
Ground (0V)
2
CSI_D_D0_N
CSI-2 D data lane 0
3
CSI_D_D0_P
CSI-2 D data lane 0
4
GND
Ground (0V)
5
CSI_D_D1_N
CSI-2 D data lane 1
6
CSI_D_D1_P
CSI-2 D data lane 1
7
GND
Ground (0V)
8
CSI_D_CLK_N
CSI-2 D clock
9
CSI_D_CLK_P
CSI-2 D clock
10
GND
Ground (0V)
11
CAM_D_PWDN
12
CAM_D_MCLK
13
I2C_SCL_3
I2C clock (3.3V level)
14
I2C_SDA_3
I2C data (3.3V level)
15
3.3V
V3.3 power out
1
GND
Ground (0V)
2
CSI_E_D0_N
CSI-2 E data lane 0
3
CSI_E_D0_P
CSI-2 E data lane 0
4
GND
Ground (0V)
5
CSI_E_D1_N
CSI-2 E data lane 1
6
CSI_E_D1_P
CSI-2 E data lane 1
7
GND
Ground (0V)
8
CSI_E_CLK_N
CSI-2 E clock
9
CSI_E_CLK_P
CSI-2 E clock
10
GND
Ground (0V)
11
CAM_E_PWDN
12
CAM_E_MCLK
13
I2C_SCL_2
I2C clock (3.3V level)
14
I2C_SDA_2
I2C data (3.3V level)
15
3.3V
V3.3 power out
1
GND
Ground (0V)
2
CSI_F_D0_N
CSI-2 F data lane 0
3
CSI_F_D0_P
CSI-2 F data lane 0
4
GND
Ground (0V)
5
CSI_F_D1_N
CSI-2 F data lane 1
6
CSI_F_D1_P
CSI-2 F data lane 1
7
GND
Ground (0V)
8
CSI_F_CLK_N
CSI-2 F clock
9
CSI_F_CLK_P
CSI-2 F clock
10
GND
Ground (0V)
11
CAM_F_PWDN
12
CAM_F_MCLK
13
I2C_SCL_2
I2C clock (3.3V level)
14
I2C_SDA_2
I2C data (3.3V level)
15
3.3V
V3.3 power out
1
V3.3
V3.3 power out
2
DOUT
I2S audio data out (3.3V level)
3
DIN
I2S audio data in (3.3V level)
4
CLK
I2S audio bit clock (3.3V level)
5
LRCLK
I2S audio word clock (3.3V level)
6
GND
Ground (0V)
1
CSI_A_D0_P
CSI-2 A data lane 0
2
CSI_B_D0_P
CSI-2 B data lane 0
3
CSI_A_D0_N
CSI-2 A data lane 0
4
CSI_B_D0_N
CSI-2 B data lane 0
5
GND
Ground (0V)
6
GND
Ground (0V)
7
CSI_A_CLK_P
CSI-2 A clock
8
CSI_B_CLK_P
CSI-2 B clock
9
CSI_A_CLK_N
CSI-2 A clock
10
CSI_B_CLK_N
CSI-2 B clock
11
GND
Ground (0V)
12
GND
Ground (0V)
13
CSI_A_D1_P
CSI-2 A data lane 1
14
CSI_B_D1_P
CSI-2 B data lane 1
15
CSI_A_D1_N
CSI-2 A data lane 1
16
CSI_B_D1_N
CSI-2 B data lane 1
17
GND
Ground (0V)
18
GND
Ground (0V)
19
CSI_C_D0_P
CSI-2 C data lane 0
20
CSI_D_D0_P
CSI-2 D data lane 0
21
CSI_C_D0_N
CSI-2 C data lane 0
22
CSI_D_D0_N
CSI-2 D data lane 0
23
GND
Ground (0V)
24
GND
Ground (0V)
25
CSI_C_CLK_P
CSI-2 C clock
26
CSI_D_CLK_P
CSI-2 D clock
27
CSI_C_CLK_N
CSI-2 C clock
28
CSI_D_CLK_N
CSI-2 D clock
29
GND
Ground (0V)
30
GND
Ground (0V)
31
CSI_C_D1_P
CSI-2 C data lane 1
32
CSI_D_D1_P
CSI-2 D data lane 1
33
CSI_C_D1_N
CSI-2 C data lane 1
34
CSI_D_D1_N
CSI-2 D data lane 1
35
GND
Ground (0V)
36
GND
Ground (0V)
37
CSI_E_D0_P
CSI-2 E data lane 0
38
CSI_F_D0_P
CSI-2 F data lane 0
39
CSI_E_D0_N
CSI-2 E data lane 0
40
CSI_F_D0_N
CSI-2 F data lane 0
41
GND
Ground (0V)
42
GND
Ground (0V)
43
CSI_E_CLK_P
CSI-2 E clock
44
CSI_F_CLK_P
CSI-2 F clock
45
CSI_E_CLK_N
CSI-2 E clock
46
CSI_F_CLK_N
CSI-2 F clock
47
GND
Ground (0V)
48
GND
Ground (0V)
49
CSI_E_D1_P
CSI-2 E data lane 1
50
CSI_F_D1_P
CSI-2 F data lane 1
51
CSI_E_D1_N
CSI-2 E data lane 1
52
CSI_F_D1_N
CSI-2 F data lane 1
53
GND
Ground (0V)
54
GND
Ground (0V)
55
DVDD_CAM_LV_1
Not connected
56
DVDD_CAM_LV_2
Not connected
57
DVDD_CAM_LV_1
Not connected
58
DVDD_CAM_LV_2
Not connected
59
SNN_UART_PRESENT
Not connected
60
SNN_PIN60
Not connected
61
SNN_UART_TX
Not connected
62
SNN_SPI_SCK
Not connected
63
SNN_UART_RX
Not connected
64
SNN_SPI_DIN
Not connected
65
SNN_UART_CTS
Not connected
66
SNN_SPI_CS0
Not connected
67
SNN_UART_RTS
Not connected
68
SNN_SPI_DOUT
Not connected
69
GND
Ground (0V)
70
GND
Ground (0V)
71
SNN_DMIC_CLK
Not connected
72
SNN_I2S_CLK
73
SNN_DMIC_DAT
Not connected
74
SNN_I2S_LRCLK
75
CAM_I2C3_SCL
76
SNN_I2S_SDIN
77
CAM_I2C3_SDA
78
SNN_I2S_SDOUT
79
GND
Ground (0V)
80
GND
Ground (0V)
81
VDD_CAM_FQ_HV_CAM
Not connected
82
AVDD_CAM
Not connected
83
VDD_CAM_FQ_HV_CAM
Not connected
84
VDD_AF
Not connected
85
CAM_AF_PWDN
Not connected
86
CAM_VSYNC
Not connected
87
CAM_I2C2_SCL
88
SNN_CAM1_MCLK
Not connected
89
CAM_I2C2_SDA
90
SNN_CAM1_PWDN
Not connected
91
CAMFQ_MCLK
Not connected
92
SNN_CAM1_RST
Not connected
93
CAMFQ_PWDN
Not connected
94
SNN_CAM2_MCLK
Not connected
95
CAM_RST
Not connected
96
SNN_CAM2_PWDN
Not connected
97
SNN_FLASH_EN
Not connected
98
SNN_CAM2_RST
Not connected
99
GND
Ground (0V)
100
GND
Ground (0V)
101
DVDD_CAM_IO_1V2
Not connected
102
DVDD_CAM_IO_1V8
1.8V power supply
103
SNN_FLASH_MASK
Not connected
104
SNN_TORCH_EN
Not connected
105
CAM_I2C1_SCL
106
SNN_FLASH_STROBE
Not connected
107
CAM_I2C1_SDA
108
VDD_3V3_SLP
Not connected
109
VDD_IR
Not connected
110
VDD_3V3_SLP
Not connected
111
IR_READY
Not connected
112
SNN_GYRO_INT
Not connected
113
IR_TRIGGER
Not connected
114
SNN_IR_EN
Not connected
115
GND
Ground (0V)
116
GND
Ground (0V)
117
CAM_INTR
Not connected
118
VDD_SYS
5V power supply
119
VDD_SYS_EN
Not connected
120
VDD_SYS
5V power supply
This page is only for experienced users. It requires knowledge and experience about the following topics:
Kernel development
Devicetree syntax
The Nvidia forum and its documentation about the Jetson family is a good way to get started with those kinds of work. You may start with taking a look at the Camera Adaption Guide from Nvidia.
Auvidea can also provide a quote, if you need a custom devicetree for your CSI camera on the J20, if needed. Contact sales@auvidea.eu or support@auvidea.eu for more information.
The GPIO expander populated on the J20 is used to control the mclock
and power-down
GPIO's on each CSI connector. Auvidea recommends implementing this chip in the Devicetree as GPIO-Chip in order to use those GPIO's directly as reset-gpio
in the camera device node.
GPIO | Note |
---|---|
Represented in the device tree for the AGX Orin would look like this:
Each camera node (if the driver supports this feature) contains a reset-gpio that can be assinged to one of the implemented GPIO's in the code above. An example usage of one of those GPIO's can be found in the following code in the reset-gpio
property.
The following documentation assumes that you are comfortable with the CSI/VI interface from the Nvidia Jetson family
The following example CSI/VI devicetree would implement the J20 on the AGX Orin Devkit
The TX1-Devkit uses a different CSI-Lanes than the AGX-Xavier and AGX-Orin Devkit as shown above. -> There might be some differences in the Devicetree implementation for the AGX-Orin Devkit.
P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
---|---|---|---|---|---|---|---|
P8 | P9 | P10 | P12 | P11 | P10 | P9 | P8 |
---|---|---|---|---|---|---|---|
P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
---|---|---|---|---|---|---|---|
P8 | P9 | P10 | P12 | P11 | P10 | P9 | P8 |
---|---|---|---|---|---|---|---|
P15
CAM_A_PWDN
P14
CAM_B_PWDN
P13
CAM_A_MCLK
P12
CAM_B_MCLK
P11
CAM_C_PWDN
P10
CAM_D_PWDN
P9
CAM_C_MCLK
P8
CAM_D_MCLK
P7
CAM_E_PWDN
P6
CAM_F_PWDN
P5
CAM_E_MCLK
P4
CAM_F_MCLK
P3
Not connected
P2
Not connected
P1
Not connected
P0
LED_GPIO
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1